This invention relates, in general, to microprocessors, and more particularly, to those microprocessors having an on-chip random access memory (RAM).
Microprocessors have gained wide acceptance and have proven very useful in many applications. In most cases, a microprocessor is used in conjunction with external memories which contain instructions and op-codes. Advances in LSI techniques have allowed inclusion of memories on the same chip as a microprocessor; however, the memories had limited utility since they were mainly used for temporary storage of data. It would be highly desirable to have a random access memory (RAM) located on the same integrated circuit chip as the microprocessor and interconnected in a manner to allow data from the RAM to be inputted onto the internal microprocessor data bus. In addition, in many applications it is desirable to be able to retain some of the information contained in the RAM when the microprocessor power is down. This is particularly true of microprocessors used in automobiles.
It is an object of the present invention to provide a RAM address enable circuit which inhibits the RAM address decoder at the trailing edge of a signal derived from a microprocessor clock.
Another object of the present invention is to virtually eliminate instability problems of a RAM caused by charge splitting and coupling and by multiple select and deselect.